1. Field of the Invention
The present invention relates in general to integrated semiconductor devices and more particularly to the fabrication of metal oxide semiconductor field effect transistors with raised source and drain regions and the resulting structure.
2. Description of the Prior Art
As metal oxide semiconductor field effect transistors (MOSFETs) are scaled down to have feature sizes below 0.5 microns (.mu.m), several device characteristics become increasingly important.
One important characteristic is the punchthrough voltage between the source and drain, i.e. the source/drain voltage at which conduction between the source and drain (punchthrough) occurs when the gate is biased below (above) the threshold voltage for N-channel (P-channel) MOSFETs. Punchthrough occurs as a result of a drain depletion layer extending from the drain into the channel. One conventional method of preventing punchthrough is to form the MOSFET with a channel length (distance between the source and drain) sufficient to prevent the drain depletion layer from extending across the channel. However, it is desirable to reduce the channel length to reduce the substrate surface area occupied by the MOSFET thereby allowing higher density devices to be fabricated.
One conventional method of reducing the channel length while maintaining sufficient punchthrough protection is to reduce the junction depth of the source/drain in the substrate. De La Moneda, U.S. Pat. No. 4,016,587 (hereinafter De La Moneda), teaches a raised source and drain IGFET device having shallow source/drain junctions in the substrate. Referring to FIG. 1i of De La Moneda, a raised source protrusion 13 and drain protrusion 15 are illustrated. Also shown in FIG. 1i are source junctions 17 and 22 and drain junctions 19 and 24 formed in a silicon wafer 2.
After formation of source protrusion 13, drain protrusion 15 and the respective junctions 17, 22 and 19, 24, an oxide layer 34 is grown over all the exposed silicon surfaces to insure that gate 9, source protrusion 13 and drain protrusion 15 are electrically isolated from field shields 7 and 11 and from each other. However, during the thermal cycle in which oxide layer 34 is grown, junctions 17, 22 and 19, 24 are driven substantially deeper into substrate 2. This excessive dopant diffusion undesirably degrades punchthrough protection. Further, the method taught by De La Moneda is complex and requires numerous fabrication steps. Yet, it is desirable to reduce the number of fabrication steps and to simplify the process used to produce the MOSFET.
Another conventional method of reducing the junction depth of the source/drain in the substrate is to grow a selective epitaxial layer and dope this selective epitaxial layer to form elevated source and drain regions as taught by Hsu et al. (Hsu), U.S. Pat. No. 5,504,031. Referring to Hsu FIG. 12, a selective epitaxial layer is grown and doped to form n-channel elevated source/drain regions 34 extending from sidewalls 22 to field oxide regions 12 and p-channel elevated source/drain regions 40 extending from sidewalls 26 to field oxide regions 12. However, the present inventors have discovered that faceting of the selective epitaxial layer unpredictably increases the junction depth of the source/drain in the substrate.
Present FIG. 1 is a cross-sectional view a portion of a MOSFET having a selective epitaxial layer illustrating the problem of faceting. Referring to FIG. 1, during growth of epitaxial layer 10, a growth plane 12 (growth along a different crystallographic plane than the principal surface of the epitaxial layer) is formed where epitaxial layer 10 meets sidewall spacer 14. The formation of growth plane 12 is well known to those skilled in the art and is commonly referred to as faceting. As a result of faceting, epitaxial layer 10 is thinner where epitaxial layer 10 meets sidewall spacer 14. Implanted impurities readily pass through this thinner portion of epitaxial layer 10 into substrate 16 compared to the thicker portions of epitaxial layer 10. Thus, the junction depth of the source/drain in the substrate is greatest near the channel (and sidewall spacer 14) which degrades punchthrough protection. Accordingly, it is desirable to have a method of forming a MOSFET which does not use a selective epitaxial layer growth technique.
Another important device characteristic is the threshold voltage, i.e. the voltage applied to the conductive gate layer at which the channel between the source and drain becomes conductive. Among other things, the threshold voltage is determined in part by the source/drain voltage (the voltage between the source and drain). However, it is desirable to minimize variations in the threshold voltage from variations in the source/drain voltage, i.e. to control the conduction of the channel by the voltage applied to the conductive gate layer independent of the source/drain voltage.
One conventional method of reducing the effect on threshold voltage of the source/drain voltage is to reduce the junction depth of the source/drain in the substrate. However, as discussed above, conventional techniques provide only a limited reduction in the junction depth of the source/drain in the substrate.
Other obstacles in scaling down MOSFETs to feature sizes below 0.5 .mu.m are the limitations in conventional photolithographic masking techniques and particularly the inability to precisely pattern the mask, i.e. the tolerance associated with positioning the mask. To accommodate photolithographic masking tolerance of each masking step, the feature size of the MOSFET must be increased to insure reliability of the MOSFET which limits reduction in feature size. Accordingly, it is desirable to fabricate MOSFETs using the fewest number of photolithographic masking steps to reduce feature size.
The art needs a method of fabricating MOSFETs with a junction depth of the source/drain in the substrate which is sufficiently shallow to provide adequate punchthrough protection and threshold voltage control in MOSFETs with reduced feature size. Further, the method should minimize the number of photolithographic masking steps used, to allow further reductions in feature size.